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EL4584C february 1995 rev b EL4584C horizontal genlock, 4 f sc note: all information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a ``controlled document''. current revisions, if any, to these specifications are maintained at the factory and are available upon your request. we recommend checking the revision level before finalization of your design documentation. y 4584c ? 1994 elantec, inc. features # 36 mhz, general purpose pll # 4f sc based timing (use the el4585 for 8 f sc ) # compatible w/el4583 sync separator # vcxo, xtal, or lc tank oscillator # k 2 ns jitter (vcxo) # user controlled pll capture and lock # compatible with ntsc and pal tv formats # 8 pre-programmed tv scan rate clock divisors # selectable external divide for custom ratios # single 5v, low current operation applications # pixel clock regeneration # video compression engine (mpeg) clock generator # video capture or digitization # pip (picture in picture) timing generator # text or graphics overlay timing ordering information part no. temp. range package outline y EL4584Cn -40 cto a 85 c 16-pin dip mdp0031 EL4584Cs -40 cto a 85 c 16-lead so mdp0027 for 6fsc and 8fsc clock frequencies, see el4585 datasheet. demo board a demo pcb is available for this product. request ``el4584/5 demo board''. general description the EL4584C is a pll (phase lock loop) sub system, designed for video applications but also suitable for general purpose use up to 36 mhz. in a video application this device generates a ttl/cmos compatible pixel clock (clk out) which is a multi- ple of the tv horizontal scan rate, and phase locked to it. the reference signal is a horizontal sync signal, ttl/cmos format, which can be easily derived from an analog composite video signal with the el4583 sync separator. an input signal to ``coast'' is provided for applications were periodic distur- bances are present in the reference video timing such as vtr head switching. the lock detector output indicates correct lock. the divider ratio is four ratios for ntsc and four similar ratios for the pal video timing standards, by external selection of three control pins. these four ratios have been selected for com- mon video applications including 4 f sc ,3f sc , 13.5 mhz (ccir 601 format) and square picture elements used in some workstation graphics. to generate 8 f sc ,6f sc , 27 mhz (ccir 601 format) etc. use the el4585, which includes an additional divide by 2 stage. for applications where these frequencies are inappropriate or for general purpose pll applications the internal divider can be bypassed and an external divider chain used. frequencies and divisors function 3fsc ccir 601 square 4fsc divisor 851 864 944 1135 pal fosc (mhz) 13.301 13.5 14.75 17.734 divisor 682 858 780 910 ntsc fosc (mhz) 10.738 13.5 12.273 14.318 ccir 601 divisors yield 720 pixels in the portion of each line for ntsc and pal. square pixels format gives 640 pixels for ntsc and 768 pixels for pal in the active portion. 3fsc numbers do not yield integer divisors. connection diagram el4584 so, p-dip packages 4584 17
EL4584C horizontal genlock, 4 f sc absolute maximum ratings (t a e 25 c) v cc supply 7v operating junction temp 125 c storage temperature b 65 cto a 150 c power dissipation 400 mw lead temperature 260 c oscillator frequency 36 mhz pin voltages b 0.5v to v cc a 0.5v operating ambient temperature range b 40 cto a 85 c important note: all parameters having min/max specifications are guaranteed. the test level column indicates the specific device testing actually performed during production and quality inspection. elantec performs most electrical tests using modern high-speed automatic test equipment, specifically the ltx77 series system. unless otherwise noted, all tests are pulsed tests, therefore t j e t c e t a . test level test procedure i 100% production tested and qa sample tested per qa test plan qcx0002. ii 100% production tested at t a e 25 c and qa sample tested at t a e 25 c, t max and t min per qa test plan qcx0002. iii qa sample tested per qa test plan qcx0002. iv parameter is guaranteed (but not tested) by design and characterization data. v parameter is typical value at t a e 25 c for information purposes only. dc electrical characteristics (v dd e 5v, t a e 25 c unless otherwise noted) parameter conditions temp min typ max test units level i dd v dd e 5v (note 1) 25 c24ima v il input low voltage 25 c 1.5 i v v ih input high voltage 25 c 3.5 i v i il input low current all inputs except coast, v in e 1.5v 25 c b 100 i na i ih input high current all inputs except coast, v in e 3.5v 25 c 100 i na i il input low current coast pin, v in e 1.5v 25 c b 100 b 60 i m a i ih input high current coast pin, v in e 3.5v 25 c 60 100 i m a v ol output low voltage lock det, i ol e 1.6ma 25 c 0.4 i v v oh output high voltage lock det, i oh eb 1.6ma 25 c 2.4 i v v ol output low voltage clk, i ol e 3.2ma 25 c 0.4 i v v oh output high voltage clk, i oh eb 3.2ma 25 c 2.4 i v v ol output low voltage osc out, i ol e 200 m a25 c 0.4 i v v oh output high voltage osc out, i oh eb 200 m a25 c 2.4 i v i ol output low current filter out, v out e 2.5v 25 c 200 300 i m a i oh output high current filter out, v out e 2.5v 25 c b 300 b 200 i m a i ol /i oh current ratio filter out, v out e 2.5v 25 c 1.05 1.0 0.95 i i leak filter out coast mode, v dd l v out l 0v 25 c b 100 g 1 100 i na note 1: all inputs to 0v, coast floating. 2 td is 3.5in
EL4584C horizontal genlock, 4 f sc ac electrical characteristics (v dd e 5v, t a e 25 c unless otherwise noted) parameter conditions temp min typ max test units level vco gain @ 20 mhz test circuit 1 25 c 15.5 v db h-sync s/n ratio v dd e 5v (note 2) 25 c35 v db jitter vcxo oscillator 25 c1 vns jitter lc oscillator (typ) 25 c10 vns note 2: noisy video signal input to el4583c, h-sync input to EL4584C. test for positive signal lock. pin description pin no. pin name function 16,1,2 prog a,b,c digital inputs to select d n value for internal counter. see table below for values. 3 osc/vco out output of internal inverter/oscillator. connect to external crystal or lc tank vco circuit. 4v dd (a) analog positive supply for oscillator, pll circuits. 5 osc/vco in input from external vco. 6v ss (a) analog ground for oscillator, pll circuits. 7 charge pump out connect to loop filter. if the h-sync phase is leading or h-sync frequency l clk d n, current is pumped into the filter capacitor to increase vco frequency. if h-sync phase is lagging or frequency k clk d n, current is pumped out of the filter capacitor to decrease vco frequency. during coast mode or when locked, charge pump goes to a high impedance state. 8 div select divide select input. when high, the internal divider is enabled and ext div becomes a test pin, outputting clk d n. when low, the internal divider is disabled and ext div is an input from an external d n. 9 coast tri-state logic input. low( k (/3 * v cc ) e normal mode, hi z(or (/3 to )/3 * v cc ) e fast lock mode, high( l )/3 * v cc ) e coast mode. 10 h-sync in horizontal sync pulse (cmos level) input. 11 v dd (d) positive supply for digital, i/o circuits. 12 lock det lock detect output. low level when pll is locked. pulses high when out of lock. 13 ext div external divide input when div sel is low, internal d n output when div sel is high. 14 v ss (d) ground for digital, i/o circuits. 15 clk out buffered output of the vco. vco divisors table 1 prog a prog b prog c div value pin 16 pin 1 pin 2 n 0 0 0 851 0 0 1 864 0 1 0 944 0 1 1 1135 1 0 0 682 1 0 1 858 1 1 0 780 1 1 1 910 3 td is 3.5in tab wide td is 3.5in
EL4584C horizontal genlock, 4 f sc timing diagrams pll locked condition (phase error e 0) 4584 2 falling edge of h-sync a 110 ns locks to rising edge of ext div signal. out of lock condition i e e t i t h c 360 t h e h-sync period t i e phase error period 4584 3 test circuit 1 4584 5 4
EL4584C horizontal genlock, 4 f sc typical performance curves idd vs fosc 4584 4 4584 osc gain @ 20 mhz vs temp 4584 6 typical varactor 4584 7 osc gain vs fosc 4584 8 charge pump duty cycle vs i e 4584 9 5
EL4584C horizontal genlock, 4 f sc block diagram 4584 1 6
EL4584C horizontal genlock, 4 f sc description of operation the horizontal sync signal (cmos level, falling leading edge) is input to h-sync input (pin 10). this signal is delayed about 110 ns, the falling edge of which becomes the reference to which the clock output will be locked. (see timing dia- grams.) the clock is generated by the signal on pin 5, osc in. there are 2 general types of vco that can be used with the EL4584C, lc and crys- tal controlled. additionally, each type can be ei- ther built up using discrete components, includ- ing a varactor as the frequency controlling ele- ment, or complete, self contained modules can be purchased with everything inside a metal can. the modules are very forgiving of pcb layout, but cost more than discrete solutions. the vco or vcxo is used to generate the clock. an lc tank resonator has greater ``pull'' than a crystal controlled circuit, but will also be more likely to drift over time, and thus will generate more jit- ter. the ``pullability'' of the circuit refers to the ability to ``pull'' the frequency of oscillation away from its center frequency by modulating the volt- age on the control pin of a vco module or varac- tor, and is a function of the slope and range of the capacitance-voltage curve of the varactor or vco module used. the vco signal is sent to a divide by n counter, and to the clk out pin. the divisor n is determined by the state of pins 1,2, and 16 and is described in table 1 above. the di- vided signal is sent, along with the delayed h-sync input, to the phase/frequency detector, which compares the two signals for phase and frequency differences. any phase difference is converted to a current at the charge pump output filter (pin 7). a vco with positive frequency deviation with control voltage must be used. va- ractors have negative capacitance slope with voltage, resulting in positive frequency deviation with control voltage for the oscillators in figures 10 and 11 below. vco the vco should be tuned so its frequency of os- cillation is very close to the required clock output frequency when the voltage on the varactor is 2.5 volts. vcxo and vco modules are already tuned to the desired frequency, so this step is not neces- sary if using one of these units. the range of the charge pump output (pin 7) is 0 to 5 volts and it can source or sink a maximum of about 300 m a, so all frequency control must be accomplished with variable capacitance from the varactor with- in this range. crystal oscillators are more stable than lc oscillators, which translates into lower jitter, but lc oscillators can be pulled from their mid-point values further, resulting in a greater capture and locking range. if the incoming hori- zontal sync signal is known to be very stable, then a crystal oscillator circuit can be used. if the h-sync signal experiences frequency variations of greater than about 300 ppm, an lc oscillator should be considered, as crystal oscillators are very difficult to pull this far. when h-sync in- put frequency is greater than clk frequen- cy d n, charge pump output (pin 7) sources cur- rent into the filter capacitor, increasing the volt- age across the varactor, which lowers its capaci- tance, thus tending to increase vco frequency. conversely, filter output pulls current from the filter capacitor when h-sync frequency is less than clk d n, forcing the vco frequency lower. loop filter the loop filter controls how fast the vco will respond to a change in filter output stimulus. its components should be chosen so that fast lock can be achieved, yet with a minimum of vco ``hunting'', preferably in one to two oscillations of charge pump output, assuming the vco fre- quency starts within capture range. if the filter is under-damped, the vco will over and under- shoot the desired operating point many times be- fore a stable lock takes place. it is possible to under-damp the filter so much that the loop itself oscillates, and vco lock is never achieved. if the filter is over-damped, the vco response time will be excessive and many cycles will be required for a lock condition. over-damping is also character- ized by an easily unlocked system because the filter can't respond fast enough to perturbations in vco frequency. a severely over damped sys- tem will seem to endlessly oscillate, like a very large mass at the end of a long pendulum. due to parasitic effects of pcb traces and component variables, it will take some trial and error experi- mentation to determine the best values to use for any given situation. use the component tables as a starting point, but be aware that deviation from these values is not out of the ordinary. 7
EL4584C horizontal genlock, 4 f sc description of operation e contd. external divide div sel (pin 8) controls the use of the internal divider. when high, the internal divider is en- abled and ext div (pin 13) outputs the clk out divided by n. this is the signal to which the horizontal sync input will lock. when divide se- lect is low, the internal divider output is disabled, and external divide becomes an input from an ex- ternal divider, so that a divisor other than one of the 8 pre-programmed internal divisors can be used. normal mode normal mode is enabled by pulling coast (pin 9) low (below (/3 * v cc ). if h-sync and clk d n have any phase or frequency difference, an error signal is generated and sent to the charge pump. the charge pump will either force current into or out of the filter capacitor in an attempt to modu- late the vco frequency. modulation will contin- ue until the phase and frequency of clk d n ex- actly match the h-sync input. when the phase and frequency match (with some offset in phase that is a function of the vco characteristics), the error signal goes to zero, lock detect no longer pulses high, and the charge pump enters a high impedance state. the clock is now locked to the h-sync input. as long as phase and frequency differences remain small, the pll can adjust the vco to remain locked and lock detect remains low. fast lock mode fast lock mode is enabled by either allowing coast to float, or pulling it to mid supply (be- tween (/3 and )/3 * v cc ). in this mode, lock is achieved much faster than in normal mode, but the clock divisor is modified on the fly to achieve this. if the phase detector detects an error of enough magnitude, the clock is either inhibited or reset to attempt a ``fast'' lock of the signals. forcing the clock to be synchronized to the h- sync input this way allows a lock in approximate- ly 2 h-cycles, but the clock spacing will not be regular during this time. once the near lock con- dition is attained, charge pump output should be very close to its lock-on value and placing the device into normal mode should result in a nor- mal lock very quickly. fast lock mode is intend- ed to be used where h-sync becomes irregular, until a stable signal is again obtained. coast mode coast mode is enabled by pulling coast (pin 9) high (above )/3 * v cc ). in coast mode the internal phase detector is disabled and filter out remains in high impedance mode to keep filter out volt- age and vco frequency as constant a possible. vco frequency will drift as charge leaks from the filter capacitor, and the voltage changes the vco operating point. coast mode is intended to be used when noise or signal degradation result in loss of horizontal sync for many cycles. the phase detector will not attempt to adjust to the resultant loss of signal so that when horizontal sync returns, sync lock can be re-established quickly. however, if much vco drift has oc- curred, it may take as long to re-lock as when restarting. lock detect lock detect (pin 12) will go low when lock is es- tablished. any dc current path from charge pump out will skew ext div relative to h-sync in, tending to offset or add to the 110 ns internal delay, depending on which way the extra current is flowing. this offset is called static phase error, and is always present in any pll system. if, when the part stabilizes in a locked mode, lock detect is not low, adding or subtract- ing from the loop filter series resistor r 2 will change this static phase error to allow ldet to go low while in lock. the goal is to put the rising edge of ext div in sync with the falling edge of h-sync a 110 ns. (see timing diagrams.) in- creasing r 2 decreases phase error, while decreas- ing r 2 increases phase error. (phase error is posi- tive when ext div lags h-sync.) the resist- ance needed will depend on vco design or vcxo module selection. 8
EL4584C horizontal genlock, 4 f sc applications information choosing external components 1. to choose lc vco components, first pick the desired operating frequency. for our example we will use 14.31818 mhz, with an h-sync fre- quency of 15.734 khz. 2. choose a reasonable inductor value (10 20 m h works well). we choose 15 m h. 3. calculate c t needed to produce f osc . f osc e 1 2 q 0 lc t c t e 1 4 q 2 f 2 l e 1 4 q 2 (14.318e6) 2 (15e b 6) e 8.2 pf 4. from the varactor data sheet find c v @ 2.5v, the desired lock voltage. c v e 23 pf for our smv1204-12, for example. 5. c 2 should be about 10c v , so we choose c 2 e 220 pf for our example. 6. calculate c 1 . since c t e c 1 c 2 c v (c 1 c 2 ) a (c 1 c v ) a (c 2 c v ) , then c 1 e c 2 c t c v (c 2 c v ) b (c 2 c t ) b (c t c v ) . for our example, c 1 e 14 pf. (a trim cap may be used for fine tuning.) examples for each frequen- cy using the internal divider follow. typical application horizontal genlock provides clock for an analog to digital converter, digitizing analog video. typical lc vco 4584 10 figure 10 lc vco component values (approximate) frequency l1 c1 c2 (mhz) ( m h) (pf) (pf) 13.301 15 18 220 13.5 15 17 220 14.75 12 18 220 17.734 12 10 220 10.738 22 20 220 12.273 18 17 220 14.318 15 14 220 note: use shielded inductors for optimum performance. typical xtal vco 4584 11 figure 11 4584 18 9
EL4584C horizontal genlock, 4 f sc xtal vco component values (approximate) frequency r1 c1 c2 (mhz) (k x ) (pf) (uf) 13.301 300 15 .001 13.5 300 15 .001 14.75 300 15 .001 17.734 300 15 .001 10.738 300 15 .001 12.273 300 15 .001 14.318 300 15 .001 the above oscillators are arranged as colpitts os- cillators, and the structure is redrawn here to em- phasize the split capacitance used in a colpitts oscillator. it should be noted that this oscillator configuration is just one of literally hundreds possible, and the configuration shown here does not necessarily represent the best solution for all applications. crystal manufacturers are very in- formative sources on the design and use of oscil- lators in a wide variety of applications, and the reader is encouraged to become familiar with them. colpitts oscillator 4584 12 c 1 is to adjust the center frequency, c 2 dc iso- lates the control from the oscillator, and v1 is the primary control device. c 2 should be much larger than c v so that v 1 has maximum modulation capability. the frequency of oscillation is given by: f e 1 2 q 0 lc t c t e c 1 c 2 c v (c 1 c 2 ) a (c 1 c v ) a (c 2 c v ) choosing loop filter components the pll, vco, and loop filter can be described as: 4584 13 where: k d e phase detector gain in a/rad f(s) e loop filter impedance in v/a k vco e vco gain in rad/s/v n e internal or external divisor it can be shown that for the loop filter shown below: c 3 e k d k vco n 0 2 n ,c 4 e c 3 10 ,r 3 e 2n g 0 n k d k vco where 0 n e loop filter bandwidth, and g e loop filter damping factor. 1. k d e 300 m a/2 q rad e 4.77e-5a/rad for the EL4584C. 2. the loop bandwidth should be about h-sync frequency/20, and the damping ratio should be 1 for optimum performance. for our example, 0 n e 15.734 khz/20 e 787 hz & 5000 rad/s. 3. n e 910 from table 1. n e vcofrequency h-syncfrequency e 14.31818m 15.73426k e 910 4. k vco represents how much the vco frequen- cy changes for each volt applied at the control pin. it is assumed (but probably isn't) linear about the lock point (2.5v). its value depends on the vco configuration and the varactor 10
EL4584C horizontal genlock, 4 f sc transfer function c v e f(v c ), where v c is the reverse bias control voltage, and c v is varactor capacitance. since f(v c ) is nonlinear, it is probably best to build the vco and measure k vco about 2.5v. the results of one such mea- surement are shown below. the slope of the curve is determined by linear regression tech- niques and equals k vco . for our example, k vco e 6.05 mrad/s/v. f osc vs v c ,lcvco 4584 14 5. now we can solve for c 3 ,c 4 , and r 3 . c 3 e k d k vco n 0 2 n e (4.77e b 5)(6.05e6) (910)(5000) 2 e 0.01 m f c 4 e c 3 10 e 0.001 m f r 3 e 2n g 0 n k d k vco e (2)(910)(1)(5000) (4.77e b 5)(6.05e6) e 31.5 k x we choose r 3 e 30 k x for convenience. 6. notice r 2 has little effect on the loop filter de- sign. r 2 should be large, around 100k, and can be adjusted to compensate for any static phase error t i at lock, but if made too large, will slow loop response. if r 2 is made smaller, t i (see timing diagrams) increases, and if r 2 in- creases, t i decreases. for ldet to be low at lock, l t i l k 50 ns. c 4 is used mainly to attenu- ate high frequency noise from the charge pump. lock time let s e r 3 c 3 . as t increases, damping increases, but so does lock time. decreasing t decreases damping and speeds up loop response, but in- creases overshoot and thus increases the number of hunting oscillations before lock. critical damp- ing ( g e 1) occurs at minimum lock time. because decreased damping also decreases loop stability, it is sometimes desirable to design slightly over- damped ( g l 1), trading lock time for increased stability. typical loop filter 4584 16 lc loop filter components (approximate) frequency r2 r3 c3 c4 (mhz) (k x )(k x )( m f) ( m f) 13.301 100 30 0.01 0.001 13.5 100 30 0.01 0.001 14.75 100 33 0.01 0.001 17.734 100 39 0.01 0.001 10.738 100 22 0.01 0.001 12.273 100 27 0.01 0.001 14.318 100 30 0.01 0.001 xtal loop filter components (approximate) frequency r2 r3 c3 c4 (mhz) (k x )(m x ) (pf) (pf) 13.301 100 4.3 68 6.8 13.5 100 4.3 68 6.8 14.75 100 4.3 68 6.8 17.734 100 4.3 68 6.8 10.738 100 4.3 68 6.8 12.273 100 4.3 68 6.8 14.318 100 4.3 68 6.8 11
EL4584C horizontal genlock, 4 f sc pcb layout considerations it is highly recommended that power and ground planes be used in layout. the oscillator and filter sections constitute a feedback loop and thus care must be taken to avoid any feedback signal influ- encing the oscillator except at the control input. the entire oscillator/filter section should be sur- rounded by copper ground to prevent unwanted influences from nearby signals. use separate paths for analog and digital supplies, keeping the analog (oscillator section) as short and free from spurious signals as possible. careful attention must be paid to correct bypassing. keep lead lengths short and place bypass caps as close to the supply pins as possible. if laying out a pcb to use discrete components for the vco section, care must be taken to avoid parasitic capacitance at the osc pins 3 and 5, and filter out (pin 7). remove ground and power plane copper above and below these traces to avoid making a capacitive connection to them. it is also recom- mended to enclose the oscillator section within a shielded cage to reduce external influences on the vco, as they tend to be very sensitive to ``hand- waving'' influences, the lc variety being more sensitive than crystal controlled oscillators. in general, the higher the operating frequency, the more important these considerations are. self contained vcxo or vco modules are already mounted in a shielding cage and therefore do not require as much consideration in layout. many crystal manufacturers publish informative litera- ture regarding use and layout of oscillators which should be helpful. 12
EL4584C horizontal genlock, 4 f sc demo board 4584 19 13
EL4584C horizontal genlock, 4 f sc the vco and loop filter section of the el4583/4/5 demo board can be implemented in the following configurations: (1) vcxo 4584 20 (2) xtal 4584 21 (3) lc tank 4584 22 14
blank 15
EL4584C february 1995 rev b EL4584C horizontal genlock, 4 f sc component sources inductors # dale electronics e. highway 50 po box 180 yankton, sd 57078-0180 (605) 665-9301 crystals, vcxo, vco modules # connor-winfield 2111 comprehensive drive aurora, il 60606 (708) 851-4722 # piezo systems 100 k street po box 619 carlisle, pa 17013 (717) 249-2151 # reeves-hoffman 400 west north street carlisle, pa 17013 (717) 243-5929 # saronix 151 laura lane palo alto, ca 94043 (415) 856-6900 # standard crystal 9940 baldwin place el monte, ca 91731 (818) 443-2121 varactors # alpha industries 20 sylvan road woburn, ma 01801 (617) 935-5150 # motorola semiconductor products 2100 e. elliot tempe, az 85284 (602) 244-6900 note: these sources are provided for information purposes only. no endorsement of these compa- nies is implied by this listing. general disclaimer specifications contained in this data sheet are in effect as of the publication date shown. elantec, inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. elantec, inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. elantec, inc. 1996 tarob court milpitas, ca 95035 telephone: (408) 945-1323 (800) 333-6314 fax: (408) 945-9305 european office: 44-71-482-4596 warning e life support policy elantec, inc. products are not authorized for and should not be used within life support systems without the specific written consent of elantec, inc. life support systems are equipment in- tended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. users contemplating application of elantec, inc. products in life support systems are requested to contact elantec, inc. factory headquarters to establish suitable terms & conditions for these applications. elantec, inc.'s warranty is limited to replace- ment of defective components and does not cover injury to per- sons or property or other consequential damages. printed in u.s.a. 16

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